1. Field of the Invention
The present invention relates to a layout pattern generating apparatus and a layout pattern generating method for an element used for layout design which is a part of a manufacturing method of a semiconductor integrated circuit (LSI).
2. Description of the Related Art
Generally, in designing LSI, when a layout of basic elements such as a transistor and a resistor, which constitutes an LSI, is generated, a layout pattern is manually described on a layout drawing layer for masking process by using a drawing machine or a layout pattern is automatically described by using a layout pattern generating apparatus for generating a layout pattern by designating in advance detailed numeric values (design standard) which indicate a mask layer to be used, its structure and a relative positional relationship in the structure. A variety of layout pattern generating apparatuses have been developed, as described in Japanese Patent Kokai Publication No. 2006-330970 (Patent Document 1), for example.
However, it takes much time to manually describe a layout pattern by using the drawing machine. Moreover, drawing errors frequently occur and it takes much time to analyze the drawing errors.
Further, the conventional layout pattern generating apparatus has little versatility. Therefore, when masking process (a drawing layer to be used) varies with each process or when a different element structure or a design standard is used for each process, it is required to develop a new layout pattern generating apparatus and the development takes much time. To solve the problem, the above-identified Patent Document 1 provides a suggestion that different definition data are used in the layout pattern generating apparatus when layouts having different processing rules from each other are generated. However, there are some cases where the problem cannot be solved by changing definition data, and moreover, it takes much labor and time to generate such definition data.